Amplifier circuit

ABSTRACT

An amplifier circuit composed of two cascade-connected inverter stages, each of which consists of p channel and n channel transistors connected at their drains, n channel and p channel transistors which connect the gates of the, transistors of the first inverter to their respective drains by means of the control signal while said amplifier circuit is operated, and n channel and p channel transistors which connect the gates of both transistors of the first inverter respectively to specified potentials which set both transistors at the cut-off condition by means of the control signal while said amplifier circuit is not operated.

DESCRIPTION

1. Technical Field

This invention relates to an amplifier circuit, and in more detail to anamplifier circuit wherein a couple of inverters are cascade-connectedand the second inverter is biased so that the highest gain is obtained,by connecting the input and output terminals of the first inverterthrough a resistor (including the case where resistance is zero).

2. Background Art

A conventional amplifier circuit using a couple of inverters is shown inFIG. 1.

In FIG. 1, an input signal at the input terminal T_(I) is applied to theinput of inverter I₁ via the capacitor C₁. The input and outputterminals of inverter I, are connected via the resistor R₁. The outputof the inverter I₁ is provided to the terminal T₀ via the inverter I₂.

The relation between the input and output of each inverter forming suchan amplifier circuit is shown in FIG. 2.

In FIG. 2, A shows the relation between the input V_(I-1) and outputV_(O-1) of the inverter I₁. The input-output characteristic A of theinverter I₁ is generally expressed by a straight line since a negativefeedback loop is formed for the inverter I₁. Particularly, when theresistance R₁ is zero (0), V_(I-1) becomes equal to V_(O-1), and thecharacteristic A becomes a straight line having inclination of 45°. Onthe other hand, B shows the relation between the input V_(I-2) andoutput V_(O-2) of the inverter I₂. The gain of inverter I₂ is very highsince it has no feedback loop. As is apparent from the FIG. 1, V_(O-1)equals V_(I-2).

A point C at the intersection of both characteristics of A and Bindicates the bias point of the input of the inverter I₂, and it isshown that the point C is set to the center of the characteristic Bwhere the highest gain can be obtained by making the resistance R₁ zero.Therefore, a large variation in the output V_(O-2) can be extracted froma small change of the input V_(I-1). As explained above, an amplifiercircuit can be realized wherein the inverter is used in such a conditionthat the gain becomes the maximum. The same characteristics can easilybe provided for both inverters, for example when CMOS is used, by makingthe gain constants β of the inverters equal. By the way, fantasticprogress in the manufacturing technology of semiconductor devices haspromoted high integration of semiconductor elements to such a degreethat circuits having different functions which previously had beenformed on individual semiconductor chips are now formed on the samesemiconductor chip.

For example, consider the integrated circuits which might be used in acar radio receiver and timer (particularly a digital clock) which aremounted in a vehicle. A car radio receiver may include a phase lockedloop (generally called PLL) circuit for tuning, and this PLL circuit hasa frequency divider which converts an oscillation signal sent from acrystal controlled oscillator to the desired frequency and an inputamplifier circuit having the aforementioned construction in order togenerate a local oscillation signal.

Formation of the PLL circuit composed of circuits having differentfunctions onto the same semiconductor chip facilitates the manufactureof a car radio.

On the other hand, a clock also requires a crystal controlled oscillatorto generate a stabilized oscillation frequency and a divider forobtaining the desired frequency signal, in order to sequentially operatea counter.

Thus total construction can be simplified by using the crystalcontrolled oscillator and a part of the divider in common for both a carradio and the clock.

But, there is a large difference in how car radios and clocks are used.A car radio, for example, is switched on when the driver or other persondesires to listen to a radio program, and is switched off when he isgoing to leave the car. On the other hand, a clock must always operatewithout relation to the driver or other person's attendance, and it isglanced at only for convenience when one desires to know the presenttime.

For this reason, when using the divider circuit a PLL circuit in commonfor a car radio and timer, the power supply of the integrated circuitmust not be switched off even when a driver or other person is notlistening to the car radio.

But, if the input amplifier circuit of this PLL circuit is composed ofCMOS (Complimentary Metal Oxide Semiconductor), the p channeltransistors and n channel transistors in each inverter and the internalcircuits simultaneously become conductive, allowing a steady current toflow, so that the input amplifier circuit consumes much electrical powereven when the car radio is not operated. This is a serious disadvantagefor car electronics devices which use a battery as the power supply.

DISCLOSURE OF INVENTION

It is an object of the present invention to offer an amplifier circuitthat can reduce power consumption without switching off the power sourceof said element when it is not operated.

According to the present invention, provided is an amplifier circuitcomposed of cascade-connected first and second inverters, in each ofwhich the p channel and n channel transistors are connected in series,first and second control transistors which become conductive when aspecified control voltage is applied and which connect the gates of bothtransistors forming said first inverter to their respective drains, thethird and fourth control transistors which become conductive when saidspecified control voltage is not applied and which connect the gates ofboth transistors forming said first inverter to the power supply or theground respectively, and a fifth transistor which becomes conductivewhen said specified control voltage is not applied and which fixes thegates of both transistors forming said second inverter to the powersource or ground potential, so that power consumption can be drasticallyreduced without switching off the power supply while the amplifier isnot being operated.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 shows the construction of an existing amplifier using inverters;

FIG. 2 shows characteristics indicating the relation between the inputand output of the amplifier circuit shown in FIG. 1;

FIG. 3 shows a schematic diagram indicating the construction of anembodiment of the amplifier circuit of the present invention; and

FIG. 4 shows a schematic diagram of a radio receiver circuit wherein theamplifier circuit shown in FIG. 3 is adopted.

BEST MODE FOR CARRYING OUT THE INVENTION

A preferred embodiment of the present invention will be explainedhereunder by referring to FIG. 3.

In FIG. 3, P₁, P₂, P₃, P₄ and P₅ denote p channel transistors; N₁, N₂,N₃, N₄, N₅ and N₆ denote n channel transistors; C₁ denotes a capacitor;T₁ denotes an input terminal; T_(O) denotes an output terminal; T_(c)denotes a control terminal, V_(DD) denotes a positive power supply.

Transistors P₂, N₂ and P₃, N₃ are so configured that the gain constant βbecomes equal respectively. The transistors P₂ and N₂ operate as thefirst inverter, while the transistors P₃ and N₃ operate as the secondinverter.

The construction where the gates of transistors P₂ and N₂ of the firstinverter are connected to their respective drains is a more practicalversion of the existing amplifier circuit shown in FIG. 1. In contrastto the existing amplifier circuit, the amplifier of the presentinvention comprises first and second control transistors N₁ and P₄ whichbecome conductive when the specified control signal is applied to thecontrol terminal T_(c) and which connect the gates of transistors P₂ andN₂ (which form the first inverter to their respective drains); third andfourth control transistors P₁ and N₄ which become conductive when thespecified control signal is at a low level and which connect the gatesof transistors P₂ and N₂ (which form said first inverter) respectivelyto the power supply V_(DD) or ground; fifth transistor N₆ which becomesconductive when said control signal is at a low level and which fixesthe gates of transistors P₃ and N₃ (which form the second inverter) tothe ground potential (or power supply voltage V_(DD)); and an inverterconsisting of transistors P₅ and N₅ which operates these transistors asmentioned above.

In order to operate the circuit as shown in FIG. 3 as an amplifier, ahigh level signal is applied to the control terminal T_(c). Thereby, thetransistors N₁ and P₄ becomes conductive, connecting the gates oftransistors P₂ and N₂ to their respective drains. Therefore, the inputand output of the first inverter consisting of transistors P₂ and N₂ areconnected and thereby the input voltage becomes equal to the outputvoltage as in the case of the inverter I₁ in FIG. 1. Since the firstinverter, consisting of transistors P₂ and N₂ and the second inverter,consisting of transistors P₃ and N₃ have the same gain consistant β, thesecond inverter is so biased that the highest gain is obtained, as inthe case of the above explanation, and operates as the required inputamplifier.

To discontinue operation as an amplifier, a low level signal is appliedto the control terminal T_(c). Thereby, the output of the inverterconsisting of transistors P₅ and N₅ becomes high. Therefore, transistorsP₁ and N₄ become conductive, setting transistors N₁ and P₄ at thecut-off condition. Thus, the gates of transistors P₂ and N₂ are set atthe cut-off condition because these gates are connected to the powersource V_(DD) and ground respectively, so that a current does not flowbetween the power supply and ground via the first inverter.

Simultaneously, the transistor N₆ becomes conductive and an input of thesecond inverter, consisting of transistors P₃ and N₃, becomes low, sothat the output of the second inverter at the terminal T_(O) is fixed ata high level. Accordingly, no current flows between the power supply andground via the second inverter. Moreover, no current flows in thecircuits connected following the output terminal T_(O). The transistorN₆ prevents, as mentioned previously, current from flowing between thepower supply and ground via the second inverter, consisting oftransistors P₃ and N₃ because the potential at the interim point oftransistors P₂ and N₂ becomes unstable due to the cut-off of transistorsP₂ and N₂. Therefore, the output of the second inverter at the terminalT_(O) may alternately be set to a low level by connecting the transistorN₆ between the interim point of transistors P₂ and N₂ and the powersupply, with the input of second inverter, consisting of transistors P₃and N₃ being set at a high level while the transistor N₆ is conductive.

When the output of the terminal T_(O) is thus set at a high level or lowlevel, one of the CMOS P channel and n channel transistors is set in thecut-off condition and, in case the circuit connected following thisamplifier circuit uses CMOS, power consumption can be reduced.Accordingly, the present invention is particularly effective whenadopted into an integrated circuit device constructed by using a CMOS.

FIG. 4 is the preferred embodiment of a circuit adopting the amplifiercircuit shown in FIG. 3, and particularly a divider circuit of the PLLcircuit of a radio receiver which is used in common as a part of thedivider circuit of a clock.

The PLL circuit comprises a voltage controlled oscillator 5, inputamplifier circuit 7, program counter 8, crystal controlled oscillator 9,divider circuit 10, phase detection circuit 11 and low pass filter 12.

In the program counter 8 of the PLL circuit, when a listener selects aprogram, a signal is applied to the specified terminal according to theselected program (broadcasting station) among the terminals t₁, t₂ . . .t_(n), and the dividing ratio of the program counter is set.

The input signal is frequency-converted in accordance with the signalapplied to the terminal t₁, t₂, . . . , t_(n) by means of the programcounter and is then subjected to phase comparison at the phase detectioncircuit 11 with a signal obtained by dividing the output of crystalcontrolled oscillator 9.

If the output frequency of the voltage controlled oscillator 5 variesfrom the frequency of the specified local oscillation signal, an outputis detected from the phase detection circuit 11 and it is then given tothe voltage controlled oscillator 5 via a low pass filter 12.

Therefore, the voltage controlled oscillator 5 is controlled by saiddetected output, causing the output frequency to be shifted to thespecified local oscillation signal frequency.

Since a stable local oscillation signal is thus given to the mixer 2, abroadcast signal received through the antenna 1 is processed fordelivery to loud speaker 4 via an ordinary receiving circuit, comprisingthe mixer 2 and intermediate frequency amplifier circuit 3 etc. On theother hand, the crystal controlled oscillator 9 in this PLL circuit isalso used as the pulse generation source of a clock.

A signal sent from the crystal controlled oscillator 9 is supplied tosaid divider circuit 10, and its output is then supplied to the phasedetection circuit 11 as already been explained. The desired dividedsignal is also supplied to the divider circuit 13 and is further dividedin frequency to a 1-second clock signal which drives clock circuit 14.

Although not illustrated, in the clock circuit 14, the counter receivessaid clock signal of 1-second period and simultaneously an indicator,using liquid crystal, displays the content of counter.

If the elements of block 6, including input amplifier circuit 7, programcounter 8, divider circuits 10 and 13, phase detection circuit 11 andlow pass filter 12 are formed on the same semiconductor chip duringcircuit construction, the power source applied to the chip cannot beturned OFF because the divider circuits 10, and 13 must be operated evenwhile the radio receiver is not in use.

The amplifier circuit of the present invention shown in FIG. 3, can beused as input amplifier circuit 7 by connecting the input terminal T_(I)to the output terminal of the voltage controlled oscillator 5 while theoutput terminal T_(O) is connected to the input terminal of programcounter 8, so that the amplifier circuit can be set to a non-operativecondition by inputting a low level signal to the control terminal T_(c)when the radio is not being used in order that power consumption can bereduced without switching off the power supply.

Here, the control signal to be applied to the control terminal can beproduced by using, for example, the power switch 15 of the radioreceiver, as shown in FIG. 4. When the power switch is turned ON, themovable contact of switch 15 is set to the ON side and a power sourcevoltage V_(DD) (high level) is applied to the control terminal T_(c),while if the power switch is turned OFF, movable contact of switch 15 isset to OFF the side and a ground potential (low level) is applied to thecontrol terminal T_(c). Moreover, it is also possible to introduce othertactics in addition to the power switch, such as applying a high levelsignal to the control terminal T_(c) when the start key of the vehicleis keyed on, an applying a low level signal when the start key isremoved.

As explained above, the amplifier circuit of the present invention iscapable of exhibiting the following excellent effects: it operates as anamplifier circuit using an inverter when a high level signal is appliedto the control terminal and does not operate as an amplifier when a lowlevel signal is applied to the control terminal; it prevents unnecessarycurrent from flowing between the power supply and ground via theinverter when the amplifier circuit is not in use; and it therebyprevents unwanted power consumption when it is not operated as anamplifier.

I claim:
 1. An improved amplifier circuit of the type including acascade connection of first and second inverters, each of which consistsof series connected p channel and n channel transistors, with theamplifier having an input port connected to the input of the firstinverter for receiving a signal to be amplified and having an outputport connected to the output of the second inverter for delivering anamplified signal, wherein the improvement comprises: first means forconnecting the gates of both transistors of said first inverter to theirrespective drains when said amplifier is being operated; second meansfor connecting said gates of both transistors of said first inverter topotentials which set said both transistors of said first inverter attheir cut-off conditions when said amplifier is not operated; andcontrol port means for receiving a control signal for controlling thefirst and second means.
 2. An amplifier circuit as claimed in claim 1,further comprising third means which sets said p channel and n channeltransistors forming the second inverter at their cut-off conditionswhile said amplifier circuit is not operated.
 3. An amplifier circuit asclaimed in claim 1, wherein said first means comprises a couple oftransistors, one of which is connected between the gate of said pchannel transistor and the input line of said first inverter, the otherof which is connected between the gate of said n channel transistor andthe input line of said first inverter.
 4. An amplifier circuit asclaimed in claim 1, wherein said second means comprises a couple oftransistors connected between the gates of said p channel and n channeltransistors of said first inverter and one of the power supply andground.
 5. An amplifier circuit as claimed in claim 2, wherein saidthird means comprises a transistor connected between the input line ofsaid second inverter and one of the power supply and ground.
 6. Anamplifier circuit having an input port for receiving a signal to beamplified, an output port for delivering the amplified signal tosubsequent circuitry, and a control port for receiving a control signalto selectively render the amplifier operative and inoperative,comprising:means for receiving power from a power supply; a first pchannel transistor and a first n channel transistor series-connected, ata first intermediate connection point, between said means for receivingpower and ground; an input element and means for conveying a feedbacksignal series-connected, at a second intermediate connection point,between said input port and said first intermediate connection point; asecond p channel transistor and a second n channel transistorseries-connected, at a third intermediate connection point, between saidmeans for receiving power and said second intermediate connection point,the gate of one of said first transistors being connected to said thirdintermediate connection point and the gates of both second transistorsbeing connected to said control port; a third p channel transistor and athird n channel transistor series connected, at a fourth intermediateconnection point, between said means for receiving power and ground, thegates of both third transistors being connected to said control port; afourth p channel transistor and a fourth n channel transistor seriesconnected, at a fifth intermediate connection point, between said secondintermediate connection point and ground, the gate of the other of saidfirst transistors being connected to said fifth intermediate connectionpoint and the gates of both fourth transistors being connected to saidfourth intermediate connection point; and means connected to said firstintermediate connection point for providing an output signal at saidoutput port.
 7. The circuit of claim 6, wherein said means connected tosaid first intermediate connection point comprises a fifth p channeltransistor and a fifth n channel transistor series connected, at a sixthintermediate connection point, between said means for supplying powerand ground, said sixth intermediate connection point being connected tosaid output port and the gates of both fifth transistors being connectedto said first intermediate connection point.
 8. The circuit of claim 6or 7, further comprising an additional transistor connected between saidfirst intermediate connection point and one of said means for receivingpower and ground, the gate of said additional transistor being connectedto said fourth intermediate connection point.
 9. The circuit of claim 8,wherein said means for conveying feedback signal is a conductor.
 10. Thecircuit of claim 8, wherein said first, second, third, fourth, andadditional transistors are all fabricated on the same substrate thatadditionally includes first divider means for supplying a signal to aphase detector in a phase locked loop which includes said amplifiercircuit, and second divider means responsive to said first divider meansfor generating a signal to drive a digital clock.